STM32F时钟设置

HSE &＃61; 8MHz。
/配置前将所有RCC重置为初始值/

RCC_DeInit();/*这里选择 外部晶振&＃xff08;HSE&＃xff09;作为 时钟源&＃xff0c;因此首先打开外部晶振*/RCC_HSEConfig(RCC_HSE_ON);/*等待外部晶振进入稳定状态*/while( RCC_WaitForHSEStartUp() !&＃61; SUCCESS );/* 到这一步为止&＃xff0c;已有 HSE_VALUE &＃61; 8 MHz.PLL_VCO input clock &＃61; (HSE_VALUE or HSI_VALUE / PLL_M)&＃xff0c;根据文档&＃xff0c;这个值被建议在 1~2MHz&＃xff0c;因此我们令 PLL_M &＃61; 8&＃xff0c;即 PLL_VCO input clock &＃61; 1MHz */PLL_M &＃61; 8; /* 到这一步为止&＃xff0c;已有 PLL_VCO input clock &＃61; 1 MHz.PLL_VCO output clock &＃61; (PLL_VCO input clock) * PLL_N,这个值要用来计算系统时钟&＃xff0c;我们 令 PLL_N &＃61; 336,即 PLL_VCO output clock &＃61; 336 MHz.*/ PLL_N &＃61; 336;/* 到这一步为止&＃xff0c;已有 PLL_VCO output clock &＃61; 336 MHz.System Clock &＃61; (PLL_VCO output clock)/PLL_P ,因为我们要 SystemClock &＃61; 168 Mhz&＃xff0c;因此令 PLL_P &＃61; 2.*/PLL_P &＃61; 2;/*这个系数用来配置SD卡读写&＃xff0c;USB等功能&＃xff0c;暂时不用&＃xff0c;根据文档&＃xff0c;暂时先设为7*/PLL_Q &＃61; 7;/* 配置PLL并将其使能&＃xff0c;获得 168Mhz 的 System Clock 时钟*/RCC_PLLConfig(RCC_PLLSource_HSE, PLL_M, PLL_N, PLL_P, PLL_Q);RCC_PLLCmd(ENABLE);/*到了这一步&＃xff0c;我们已经配置好了PLL时钟。下面我们配置Syetem Clock*//*选择PLL时钟作为系统时钟源*/RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);


/到了这一步&＃xff0c;我们已经配置好了系统时钟&＃xff0c;频率为 168MHz. 下面我们可以对 AHB&＃xff0c;APB&＃xff0c;外设等的 时钟进行配置/

/*时钟的结构请参考用户手册*//*首先配置 AHB时钟&＃xff08;HCLK&＃xff09;. 为了获得较高的频率&＃xff0c;我们对 SYSCLK 1分频&＃xff0c;得到HCLK*/RCC_HCLKConfig(RCC_HCLK_Div1);/*APBx时钟&＃xff08;PCLK&＃xff09;由AHB时钟&＃xff08;HCLK&＃xff09;分频得到&＃xff0c;下面我们配置 PCLK*//*APB1时钟配置. 4分频&＃xff0c;即 PCLK1 &＃61; 42 MHz*/RCC_PCLK1Config(RCC_HCLK_Div4);/*APB2时钟配置. 2分频&＃xff0c;即 PCLK2 &＃61; 84 MHz*/RCC_PCLK2Config(RCC_HCLK_Div2);


/函数结束*/

/以上函数可以大体上说明这些库函数的作用/

}

/**

• &＃64;brief Configures the main PLL clock source, multiplication and division factors.

&＃64;简介 配置主PLL时钟源&＃xff0c;以及分频因子 (PLL不止一个,还有一个用来为音频处理提供高质量时钟)

• &＃64;note This function must be used only when the main PLL is disabled.

• &＃64;注意 这个函数只能在主PLL失能时才能使用

• &＃64;param RCC_PLLSource: specifies the PLL entry clock source.

&＃64;参数 RCC_PLLSource:选择PLL时钟源

• This parameter can be one of the following values:


这个参数可以是如下值&＃xff1a;

• &＃64;arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry


选择HSI作为PLL时钟源

• &＃64;arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry


选择HSE作为PLL时钟源

• &＃64;note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

• &＃64;param PLLM: specifies the division factor for PLL VCO input clock

&＃64;参数 PLLM&＃xff1a;设置 PLL VCO 输入时钟的 除法因子&＃xff08;division factor&＃xff09;

• This parameter must be a number between 0 and 63.


这个参数 范围是 0 ~ 63

• &＃64;note You have to set the PLLM parameter correctly to ensure that the VCO input

• frequency ranges from 1 to 2 MHz. It is recommended to select a frequency


• of 2 MHz to limit PLL jitter.


• &＃64;注意 你需要正确选择 PLLM的值&＃xff0c; 使得 VCO输入频率 介于 1~2MHz.

建议选择 2MHz 来限制PLL震荡&＃xff08;jitter&＃xff1f;&＃xff09;

• &＃64;param PLLN: specifies the multiplication factor for PLL VCO output clock

• This parameter must be a number between 192 and 432.


&＃64;参数 PLLN 选择 PLL VCO输出时钟的 乘法因子&＃xff08;multiplication factor &＃xff09;

这个参数的值 介于 192 ~432


• &＃64;note You have to set the PLLN parameter correctly to ensure that the VCO

• output frequency is between 192 and 432 MHz.


• &＃64;注意 你学要正确选PLLN的大小&＃xff0c;以保证VCO输出时钟介于 192 ~432MHz

• &＃64;param PLLP: specifies the division factor for main system clock (SYSCLK)

• This parameter must be a number in the range {2, 4, 6, or 8}.


&＃64;参数 PLLP 选择 系统时钟SYSCLK 的除法因子&＃xff08;division factor &＃xff09;&＃xff0c;这个

值可以是2,4,6,8


• &＃64;note You have to set the PLLP parameter correctly to not exceed 168 MHz on

• the System clock frequency.


• &＃64;注意 你需要正确设置PLLP&＃xff0c;确保系统时钟SYSCLK不超过168MHz

• &＃64;param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks

• This parameter must be a number between 4 and 15.


&＃64;参数 PLLQ 选择给 OTG FS(USB), SDIO(SD卡读写), RNG&＃xff08;随机数发生器&＃xff09;

时钟的除法因子&＃xff0c;其值介于4~15


• &＃64;note If the USB OTG FS is used in your application, you have to set the

• PLLQ parameter correctly to have 48 MHz clock for the USB. However,


• the SDIO and RNG need a frequency lower than or equal to 48 MHz to work


• correctly.


• &＃64;注意 如果在你的程序中用到 USB OTG FS,你需要正确设置PLLQ&＃xff0c;确保USB有

  48MHz的时钟。但是对于SDIO&＃xff0c;RNG需要一个小于或等于48MHz的时钟